Design of CMOS Inverter using SNWFET on Nanohub

AUTHOR AND
AFFILIATION

B.K. GUPTA
Department of Electronics, DDU Gorakhpur University, Gorakhpur-273009 (India)
MANISH MISHRA
Department of Electronics, DDU Gorakhpur University, Gorakhpur-273009 (India)

KEYWORDS:

Inverter, Nanotechnology, VLSI Design

Issue Date:

March 2018

Pages:

195-200

ISSN:

2319-8044 (Online) – 2231-346X (Print)

Source:

Vol.30 – No.3

PDF

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DOI:

http://dx.doi.org/10.22147/jusps-A/300304

ABSTRACT:

In this paper a layout design of an ultra-compact CMOS inverter using silicon nanowire field effect transistor with minimal power dissipation while matching the transient performance of bulk and SOI CMOS circuits is proposed. In this study, we took into account the strengths of nanotechnology including low static and dynamic power dissipation, suppression of short channel effect (SCE) and drain-to-source breakdown voltage, surface mobility enhancement and the ease of manufacturability. We analyzed different component which gives low static power dissipation. Once the body dimensions are determined, dc characteristics of the optimal n and p-channel transistors are evaluated in terms of SCE, DIBL, drain-to-source breakdown voltage and noise margin (NM). In this paper layout extraction is presented, which is a method of achieving low dynamic power dissipation.

Copy the following to cite this Article:

B. Gupta; M. Mishra, “Design of CMOS Inverter using SNWFET on Nanohub”, Journal of Ultra Scientist of Physical Sciences, Volume 30, Issue 3, Page Number 195-200, 2018


Copy the following to cite this URL:

B. Gupta; M. Mishra, “Design of CMOS Inverter using SNWFET on Nanohub”, Journal of Ultra Scientist of Physical Sciences, Volume 30, Issue 3, Page Number 195-200, 2018
Available from: http://www.ultrascientist.org/paper/1460/design-of-cmos-inverter-using-snwfet-on-nanohub


In this paper a layout design of an ultra-compact CMOS inverter using silicon nanowire field effect transistor with minimal power dissipation while matching the transient performance of bulk and SOI CMOS circuits is proposed. In this study, we took into account the strengths of nanotechnology including low static and dynamic power dissipation, suppression of short channel effect (SCE) and drain-to-source breakdown voltage, surface mobility enhancement and the ease of manufacturability. We analyzed different component which gives low static power dissipation. Once the body dimensions are determined, dc characteristics of the optimal n and p-channel transistors are evaluated in terms of SCE, DIBL, drain-to-source breakdown voltage and noise margin (NM). In this paper layout extraction is presented, which is a method of achieving low dynamic power dissipation.